The present invention relates to an improvement of a color television receiver having an automatic white control circuit.
In a conventional color television receiver of an NTSC television system, a reference white color temperature of a CRT is set to be 6,774K, for example. The reference white of the color temperature is the basis for color reproduction. Deviation between the CRT reference white color temperature and the color temperature of 6,774K results in a color misregistration between the original color of a photographed object and the color reproduced by the television receiver. Therefore, the reference white must be accurately maintained at a predetermined value.
A color CRT of the color television receiver is driven by red (R), green (G) and blue (B) signal components extracted from a composite color television signal. The CRT drive levels at the R, G and B electron guns in response to the R, G and B signal components must be accurately set at predetermined levels when the reference white is determined. When the drive biases of the respective electron guns deviate from prescribed values, an adverse effect such as a cutoff error (deviation in cutoff level) of the color CRT occurs. The cutoff error is caused by a deteriotation in electron emission of the CRT cathode due to aging and/or caused by a drift of the operating point of associated circuitries. Accordingly, a color television receiver is generally provided with a means for adjusting the bias of CRT to eliminate disadvantages due to the cutoff error.
The above bias adjusting means conventionally includes an electronic circuit with a service switch. The service switch has two switching positions. One is a "service position" and the other is a "normal position". When the service switch selects the service position, the CRT is off-circuited from a video signal and the vertical scanning is stopped. In this state, each cutoff voltage of electron guns of the CRT is set at a given value by adjusting each bias of the electron guns. Then, the CRT is properly cut off at the black level of the video signal, and the relative amplitude ratio among chrominance signals throughout the entire luminance level is properly maintained. When the bias adjustment is completed, gains of CRT drivers coupled to the respective electron guns are adjusted to predetermined values. As a result, the amplitude ratio among the R, G and B drive signals in the normal operation of the CRT becomes optimal.
The above-mentioned adjustment requires skill and experience. It is quite hard for general users to complete the above adjustment at home. When the color television receivers are used for a long period of time, the reference white becomes deviated from the prescribed value, resulting in unnatural color reproduction.
An automatic white control circuit has been recently proposed to automatically adjust the reference white even if a deterioration in the CRT cathode emission and an operating point drift in the associated circuitries occur. A typical example of such a white control circuit is shown in FIG. 1.
Referring to FIG. 1, a reference numeral 10 denotes an antenna. A television signal caught by antenna 10 is fed to a television signal processing circuit 11. Circuit 11 is generally formed of a tuner, PIF circuit, video detector, amplifier, chrominance/luminance separator, sync separator, etc. Color difference signals E11R, E11G and E11B for R-Y, G-Y and B-Y respectively appear at output terminals 11R, 11G and 11B of circuit 11. Signals E11R, E11G and E11B are supplied to matrix circuits 12R, 12G and 12G, respectively.
A video signal including a luminance signal E11Y (-Y) appears at an output terminal 11Y of circuit 11. Signal E11Y is supplied via a mixer 13 to matrix circuits 12R, 12G and 12B. In circuits 12R, 12G and 12B, luminance signal E11Y (-Y) is mixed with color diference signals E11R, E11G and E11B (R-Y, G-Y and B-Y) to produce chrominance signals E12R, E12G and E12B for R, G and B, respectively.
A blanking signal E11S containing blanket pulses BLK appears at an output terminal 11S of circuit 11. Signal E11S is supplied to a pulse separator 14. In separator 14, blanking pulses BLK are separated into a vertical blanking pulse E14V and horizontal blanking pulse E14H. Vertical and horizontal blanking pulses E14V and E14H are supplied to vertical and horizontal blanking pulse shapers 15 and 16, respectively. Shaper 15 supplies a signal E15 containing a wave-shaped vertical blanking pulse VB to a signal generator 17. Shaper 16 supplies a signal E16 containing a wave-shaped horizontal blanking pulse HB to generator 17.
A reference insertion pulse E17A appears at an output terminal 17A of generator 17. Pulse E17A is supplied to mixer 13. In mixer 13, pulse E17A is inserted in a given part, excluding a picture signal interval, of one horizontal period of video signal E11Y. The inserted reference insertion pulse E17A is supplied, together with luminance signal -Y, to matrix circuits 12R, 12G and 12B.
Chrominance signals E12R, E12G and E12B outputted from matrix circuits 12R, 12G and 12B are supplied to cathodes 21R, 21G and 21B of a color CRT 21 via level correction circuits 18R, 18G and 18B, CRT drivers 19R, 19G and 19B, and output circuits 20R, 20G and 20B, respectively. DC levels of output signals E18R, E18G and E18B from circuits 18R, 18G and 18B are increased or decreased according to DC control voltages E35R, E35G and E35B. These voltages E35R, E35G and E35B are respectively supplied to control terminals 22, 23 and 24 of circuits 18R, 18G and 18B.
Hereinafter, CRT drivers 19R, 19G and 19B are represented by CRT driver 19B. CRT driver 19B is formed of an NPN transistor 25. The base of transistor 25 receives signal E18B from level correction circuit 18B. The collector of transistor 25 is coupled via a resistor 26 to a positive voltage source Vcc, and the emitter thereof is circuit-grounded via a resistor 27. An output signal E19B from the collector of transistor 25 is supplied to output circuit 20B. The circuit arrangement of CRT drivers 19R and 19G may be the same as that of CRT driver 19B.
Output circuits 20R, 20G and 20B are similarly represented by output circuit 20B. Output circuit 20B includes a PNP transistor 28 whose base receives signal E19B from the collector of transistor 25. The collector of transistor 28 is circuit-grounded via a resistor 29, and the emitter thereof is connected to cathode 21B of CRT 21. When the current amplification factor h.sub.FE of transistor 28 is far larger than "1", a cathode current I21B flowing from cathode 21B into the emitter of transistor 28 is substantially the same as the collector current of transistor 28. In this case, the voltage drop across resistor 29 directly corresponds to the cathode current I21B. Thus, resistor 29 serves as a current detecting resistor. The arrangement of circuits 20R and 20G may be the same as that of circuit 20B.
A signal E20B corresponding to the voltage drop at resistor 29 is supplied to a sampling circuit 33B. Signals E20R and E20G being proportional to cathode currents I21R and I21G of CRT 21 are similarly supplied from circuits 20R and 20G to sampling circuits 33R and 33G, respectively. Circuits 33R, 33G and 33B may be conventional sample/hold circuits. Each of sampling circuits 33R, 33G and 33B receives a gate pulse E17B obtained from an output terminal 17B of signal generator 17. Gate pulse E17B is generated in synchronism with the generation timing of reference insertion pulse E17A (a detailed description regarding the generation timing of E17A and E17B will be made later with reference to the timing chart of FIGS. 2A to 2E).
Sampling circuit 33R samples the DC potential of signal E20R at the duration of reference insertion pulse E17A, and holds the sampled potential to provide a sampling output signal E33R. Sampling circuit 33G samples the DC potential of signal E20G at the duration of pulse E17A, and holds the sampled potential to provide a sampling output signal E33G. Sampling circuit 33B samples the DC potential of signal E20B at the duration of pulse E17A, and holds the sampled potential to provide a sampling output signal E33B.
Sampling output signals E33R, E33G and E33B are supplied to respective negative inputs (-) of comparators 35R, 35G and 35B. Each positive input (+) of comparators 35R, 35G and 35B receives a reference potential E1 from a reference potential source 36. Comparators 35R, 35G and 35B respectively supply DC control voltages E35R, E35G and E35B to control terminals 22, 23 and 24 of level correction circuits 18R, 18G and 18B. Thus, three independent negative feedback control loops for R, G and B are formed. DC control voltages E35R, E35G and E35B from comparators 35R, 35G and 35B increase when the potentials of sampling output signals E33R, E33G and E33B become lower than reference potential E1. Voltages E35R, E35G and E35B decrease when the potentials of signals E33R, E33G and E33B become higher than reference potential E1. DC control voltages E35R, E35G and E35B are converged to certain values by the DC negative feedback operation when the differences between the reference potential E1 and the respective potentials of signals E33R, E33G and E33B become zero.
Incidentally, a high voltage is applied to the anode of CRT 21 via an anode cap 40. Horizontal and vertical deflection currents are supplied via terminals 42 and 43 to a deflection coil 41. Other non-essential parts for the present invention, such as an audio circuit etc., are not illustrated.
The automatic white control circuit of FIG. 1 will operate as follows.
FIG. 2A shows a typical waveform of video signal E11Y from terminal 11Y of television signal processing circuit 11. In FIG. 2A, reference symbol VB denotes a vertical blanking pulse; HB denotes a horizontal blanking pulse; and L denotes a picture signal. FIG. 2B shows a waveform of signal E15 from vertical blanking pulse shaper 15, and FIG. 2C shows a waveform of signal E16 from horizontal blanking pulse shaper 16. Blanking pulses VB and HB shown in FIGS. 2B and 2C are supplied to signal generator 17. Reference insertion pulse E17A shown in FIG. 2D appears at output terminal 17A of signal generator 17. Pulse E17A is generated, excluding the period of picture signal L, within an interval (T1) of horizontal blanking pulse HB. Pulse E17A can be easily obtained by a conventional counter circuit with a proper gate circuit. Pulse E17A (FIG. 2D) is mixed in mixer 13 with video signal E11Y (FIG. 2A), so that a composite signal E13 (FIG. 2E) is obtained. Composite signal E13 is supplied to the respective cathodes of CRT 21 via circuit elements 12, 18, 19 and 20.
In the following description, the operation regarding the blue circuit elements represents each operation of the red, green and blue circuit elements.
Cathode current I21B from cathode 21B of CRT 21 flows into resistor 29 through the emitter-collector path of transistor 28. Resistor 29 provides a voltage drop corresponding to the magnitude of cathode current I21B, and signal E20B having a potential corresponding to the above voltage drop appears at the node between resistor 29 and the collector of transistor 28. Signal E20B is then supplied to sampling circuit 33B. Circuit 33B receives gate pulse E17B in synchronism with the generation (period T1) of reference insertion pulse E17A. Gate pulse E17B determines the timing of sampling and holding operations in circuit 33B. Sampling circuit 33B samples the potential of signal E20B and holds the sampled potential in a capacitor Cb. The sampled and held signal E33B is supplied to the negative input (-) of comparator 35B.
Comparator 35B has a characteristic as shown in FIG. 3. When the reference potential applied to the positive input (+) of comparator 35B is given to be E1 and the input and output potentials of comparator 35B are respectively plotted along the abscissa and ordinate, the output potential (E35B) decreases as the input potential (E33B) increases.
Level correction circuit 18B has such an electrical characteristic that the output DC level of signal E18B raises when DC control voltage E35B applied to control terminal 24 increases, while the output DC level of E18B falls when E35B decreases.
When the emission of cathode 21B is deteriorated (or a certain drift in the operating point of associated circuitries occurs), the corresponding cathode current I21B flowing into resistor 29 of circuit 20B becomes small. The potential of signal E33B from sampling circuit 33B is proportional to the magnitude of cathode current I21B which is obtained at the period of reference insertion pulse E17A (FIG. 2D). Since the sampling is performed only during the period T1 of reference insertion pulse E17A, the potential of signal E33B is independent of the period of picture signal L. Thus, when the deterioration of cathode emission occurs, the sampled output E33B is decreased regardless of the presence of any picture signal L.
Comparator 35B compares reference potential E1 with the potential of sampled output E33B. When a deterioration of the cathode emission occurs, comparator 35B generates DC control voltage E35B which is increased in accordance with the characteristic of FIG. 3. Then, the DC level of signal E18B from level correction circuit 18B is increased, thereby increasing the corresponding cathode current I21B.
On the contrary, when the cathode current increases, operation opposite to the operation described above is performed so as to decrease the corresponding cathode current. The increase/decrease operation point of the negative feedback control is stably converged to a point at which the difference between the reference potential E1 and the sampled output E33B becomes zero.
The cathode emission correction operation for R and G components may be performed in the same manner as that for the B component as described above. When the negative feedback control circuit is arranged to set the difference between the reference potential (E1) and the sampled output (E33) to be zero while the initial reference white is properly adjusted, the CRT biases for R, G, and B are automatically adjusted even if a deterioration in the cathode emission of CRT or a drift in the operating point of associated circuitries occurs. As a result, an automatic correction is so performed that the reference white is always maintained at a predetermined value.
The above operation will be exemplified using the circuit arrangement of the blue axis.
Assume here that the first grid (control grid) of each electron gun of CRT 21 is circuit-grounded, the voltage potential at cathode 21B and the current (I21B) flowing therethrough are respectively represented by uk and ik, and the cutoff voltage of cathode 21B is given to be Vcut. Under this assumption, cathode current ik is given as follows: EQU ik=(K/Vcut.sup.3/2)(Vcut-uk).sup.r ( 1)
where K is a proportional constant, and r is a specific constant of the CRT which is determined by the characteristic of the electron gun. Specific constant r generally falls within the range of 2.5 to 3.0.
When the input potential of comparator 35B (i.e, the potential of output E33B from sampling circuit 33B) is denoted by ui and the resistance of resistor 29 is denoted by R, input potential ui with respect to the circuit-ground is given to be: EQU ui=R.ik (2)
Further, when the potential of output E35B from comparator 35B is assumed to be uA, the sensitivity of comparator 35B is assumed to be A and the potential of reference potential source 36 is assumed to be E1, the output potential uA is given as: EQU uA=A(E1-ui) (3)
Accordingly, it can be seen than comparator 35B is a difference amplifier with a gain of A. When the potential of the signal component of reference insertion pulse E17A supplied to level correction circuit 18B is assumed to be VT1, the DC control sensitivity of circuit 18B is assumed to be B and the potential of output E18B from circuit 18B is assumed to be uB, the output potential uB is given as: EQU uB=VT1+B.uA (4)
Furthermore, when the collector potential of transistor 25 is assumed to be uc, the resistance of resistor 27 is assumed to be R1, a resistance of resistor 26 is assumed to be R2 and the potential of voltage source Vcc is given to be Vcc, the collector potential uc is given as follows: EQU uc=Vcc-(R2/R1)(uB-VBE1) (5)
where VBE1 denotes the base-emitter voltage of transistor 25. Potential uc is applied to cathode 21B via the base-emitter path of transistor 28.
A cathode potential uk at cathode 21B of CRT 21 is given as: EQU uk=uc+VBE2 (6)
where VBE2 is the base-emitter voltage of transistor 28.
When equations (2) to (5) are substituted into equation (6), the following equation is obtained: ##EQU1## Equation (7) is substituted into equation (1), so that ##EQU2## In equation (9), Vcut, Vcc, VBE1, VBE2 and R2/R1 are all constants. Accordingly, a circuit design for the configuration of FIG. 1 enables the value of .DELTA.V in equation (9) to be zero, that is, EQU .DELTA.V=0 (9')
Then, equation (10) can be rewritten as: EQU ik=(K/Vcut.sup.3/2)[(R2/R1){VT1+A.B(E1-R.ik)}].sup.r ( 11)
The cathode current ik, which nullifies the difference between input potential ui and reference potential E1 at comparator 35B, is given to be: EQU ik=E1/R
The above equation is substituted into the right term of equation (11), so that EQU ik=(K/Vcut.sup.3/2){(R2/R1)VT1}.sup.r ( 12)
Therefore, EQU ik=E1R=(K/Vcut.sup.3/2){(R2/R1)VT1}.sup.r
The above equation may be rewritten as follows: EQU E1=R.(K/Vcut.sup.3/2){(R2/R1)VT1}.sup.r ( 13)
When circuit constants VT1, Vcc, E1 and so on are selected so that equation (9') and E1 satisfy the relation of equation (13), the equation (8) holds. A current (ik)T1 flowing during the sampling period T1 (FIG. 2D) is stabilized at the following value: EQU (ik)T1=E1/R=(Ik)T1 (14)
where Ik denotes the stabilized value of cathode current ik.
Meanwhile, cutoff voltage Vcut of the electron gun of CRT 21 depends on the spatial distance between the first and second grids. Variations in the spatial distance during the fabrication of CRTs bring unfavorable variations in cutoff voltage Vcut. When equation (13) is satisfied and a variation in Vcut is given to be .DELTA.Vcut, .DELTA.V of equation (9) is given as: EQU .DELTA.V=Vcut+.DELTA.Vcut-{Vcc+VBE2+(R2/R1)VBE1} (15)
Upon the assumption of equation (9'), EQU Vcut-{Vcc+VBE2+(R2/R1)VBE1}=0
so that equation (15) is rewritten as .DELTA.V=.DELTA.Vcut. Current (ik)T1 flowing during the sampling period T1 is derived from equation (10) and it satisfies the following equation: ##EQU3## In this case, if a current error (which indicates a deviation from the target value of the cathode current) is given to be (.DELTA.ik)T1, a relation (ik)T1=(Ik)T1+(.DELTA.ik)T1 is obtained. According to equation (16), the right term of the above relation is given as: ##EQU4## A relation E1-R.(ik)T1=0 is obtained from equation (14), so that ##EQU5## if Vcut&gt;&gt;.DELTA.Vcut is satisfied and equation (17) is given to be EQU .DELTA.Vcut=(R2/R1){A.B.R(.DELTA.ik)T1}
then EQU (ik)T1+(.DELTA.ik)T1=(K/Vcut.sup.3/2){(R2/R1)VT1}.sup.r
Therefore, when the feedback control loop is arranged to satisfy the following inequality: EQU (R2/R1)A.B.R&gt;&gt;.DELTA.Vcut/(.DELTA.ik)T1 (18)
the current flowing during the sampling period T1 is kept substantially constant.
The circuit arrangement of FIG. 1 described above has the following disadvantage.
Assume that the voltage of a video signal is given to be u, that the cathode current with cutoff voltage Vcut is given to be ik, that the cathode current with cutoff voltage (Vcut+.DELTA.Vcut) is given to be ik', and that the voltage of a video signal with cutoff voltage (Vcut+.DELTA.Vcut) is given to be u+.DELTA.VT1, then cathode currents ik and ik' are given as follows: ##EQU6## Therefore, the ratio of ik' to ik is given as: ##EQU7## It is apparent that the reference white of a CRT can be fixed at a prescribed constant value when the right term of equation (21) is constant. However, it is very hard to keep the value of the right term of equation (21) constant. This is because the right term of equation (21) cannot be made constant unless a condition that .DELTA.Vcut=0 (and .DELTA.VT1=0) is satisfied. Only under this condition, does ik'/ik become constant. As previously described, cutoff voltage Vcut varies during the fabrication process of CRTs. It is almost impossible in practice to establish .DELTA.Vcut=0. Thus, a color television receiver is subjected to the variation .DELTA.Vcut, and the reference white cannot be kept constant throughout all levels (black level to white level) of the video signal.
The above problem of the prior art will be described with reference to the graphs shown in FIGS. 4 and 5. Referring to FIG. 4, voltage u of the video signal is plotted along the abscissa, and the change in ratio ik'/ik in accordance with variation .DELTA.Vcut is plotted along the ordinate. Each of curves A and B represents a change in ratio ik'/ik when variation .DELTA.Vcut occurs in the negative side with respect to Vcut (here the change of curve A in the negative side is greater than that of curve B). Each of curves D and E represents a change in ratio ik'/ik when variation Vcut occurs in the positive side with respect to Vcut (here the change of curve E in the positive side is greater than that of curve D). Curve C represents a desired ratio of ik'/ik obtained when .DELTA.Vcut=0.
As is apparent from FIG. 4, ik'/ik=1 is obtained (i.e., ratio ik'/ik becomes constant) only when .DELTA.Vcut=0. Ratio ik'/ik deviates from the center value of 1.0 according to the changes in variation .DELTA.Vcut. For instance, when the video signal voltage is set at ul in FIG. 4, ratio ik'/ik =1.1 is obtained. When the video signal voltage is set at VT1 (i.e., when the video signal voltage is represented by the voltage of reference insertion pulse E17A during the sampling period T1), ik'/ik=1 (constant) is obtained regardless of the change in .DELTA.Vcut. In other words, when the voltage of the video signal is identical with VT1, the reference white is fixed at a constant value. Otherwise, the reference white deviates from a target value, except for ik'/ik=1.0.
The deviation of the reference white will be discussed with reference to the chromaticity diagram of FIG. 5. Line f in FIG. 5 indicats a deviation in reference white of curve A in FIG. 4. Assume that R, G and B cathode currents are given by equations (19) and (20) and are respectively represented by iR, iG and iB which have a specific ratio (iR:iG:iB=1:1:1) so as to obtain the reference white W. The reference white is obtained only when the relation u=VT1 in FIG. 4 is established. For instance, when u=u1 as shown in FIG. 4 is considered, the current ratio is given to be: EQU iR:iG:iB=1:1:1.1
Then, the current ratio changes. The deviation in the reference white due to this change is represented by line f in FIG. 5.
In the course of the circuit design of a color television receiver, it is almost impossible to ensure that the reference white comes to be constant for all actual CRTs, unless the values of respective elements such as voltages and resistances in the associated circuit arrangement are carefully determined in consideration of variations in the respective CRTs. Thus, the reference white is deviated in actual commercial products due to changes in the video signal level.